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Design Examples
Pattern Matching Computation Accelerator
This flight ready, conduction cooled PMC card was designed and built for a major Aerospace firm. The customer provided the image-processing algorithm in a standard programming language and a performance specification. Datatek suggested the PMC platform, and performed the architecture and design for a Xilinx Virtex II FPGA to implement the customer’s algorithm. Datatek was responsible for the board design, schematic capture and layout in addition to the VHDL for the Xilinx design and support PLDs and associated testbench and simulation including the PCI bus core. Datatek also delivered a basic linix device driver and command line interface for unit and integration testing. The customer will be flight-testing the P1 prototypes that were delivered on time which exceeded the customer’s performance requirement.
6 Gbit/S Fast Ethernet Packet Switch
A midsize telecommunications start-up company came to Datatek to implement
a series of FPGAs for a scalable 6 Gbit/sec Fast Ethernet switch. Datatek’s
review of the customer’s specification resulted in architectural
changes that enhanced the products function. Datatek subsequently implemented
several variations of data aggregation devices. Each device moved data
to and from single high-speed ports and multiple lower speed ports using
a shared memory, pipelined architecture. The design was implemented, fully
simulated, and delivered to the customer ahead of schedule.
20 Gbit/S Crossbar Switch Controller
This FPGA Design was incorporated into the switch module of a major telecommunication
corporation’s 20 Gbit/S IP Router. This crossbar switch controller
was capable of directing 20 Gbit/sec IP traffic through an 8 x 8 crossbar
switch.
4 Mpacket/S IP Forwarding Table Lookup
Index look-up, radix tree search, and next-hop lookup algorithms were
implemented in pipelined stages to achieve a 4 Mega Packet/sec IP forwarding
table look-up function. This design required careful RTL design and synthesis
along with a high speed external memory interface to meet the demanding
search time requirements for IP lookup.
IP Packet Flow Identifier
An IP packet flow identifier was implemented to help meet the quality
of service requirement for an IP router by identifying TCP/IP traffic
flows. The device identified layer 4 traffic flows based on a set of parameters
or direct administrator input and passed the information to a scheduler
to assign priority based on quality of service commitments.
CCD Camera Controller
A scientific CCD camera maker enlisted Datatek to design and implement
their CCD controller in an Altera FPGA to reduce cost and board complexity.
The design included a CCD interface to a USB port.
SAR for Proprietary Cell Format
As part of a cost reduction effort, Datatek engineers combined serial
backplane interface ASIC and several other devices into a single Altera
PLD. The device performed the backplane contention and SAR function for
the proprietary cell switch. This device is required for every circuit
pack used in the system and therefore resulted in a substantial cost reduction
using the Altera ACEX PLD.
PCI
Interface to Optical Data Link
A PCI adaptor card designed to handle a proprietary host interface to
the telephone company’s operation systems network equipment. This
adaptor was used in critical phone system operations such as billing and
provisioning. The card interfaced a proprietary fiber interface to a standard
PCI bus on any UNIX based platform. The work included the circuit design
of the adaptor board, and the implementation of the protocol processor
in an FPGA with an interface to a PCI core.
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